Coherent Logix designs specialist chips for the defense and space sectors, but is now targeting commercial terrestrial areas, via network traffic routing and a new low-power WiFi 6E chip.
CMO Joe Fabiano outlined the history of the company and its roadmap, but the juiciest takeaway involves the much-delayed ATSC 3.0 broadcast standard.
“We started working with Sinclair Broadcasting in 2008, on what would have been ATSC 2.0, which ultimately fell apart and regrouped as ATSC 3.0. Coherent wrote the PHY and transport spec for that, so the new standard has a good chunk of our IP in there. TV manufacturers have been flouting the law and refusing to come to agreements, so that has to be worked out. We anticipate a revenue stream there,” said Fabiano.
Faultline’s neurons started firing, in a similar manner to Coherent Logix’s neuromorphic silicon designs. Why was the firm not in the newly formed Avanci Broadcast patent pool? “We withdrew from the pool. We participated in MPEG LA, but also withdrew from that. I can’t say more,” said Fabiano, which rather implied that lawyers are involved.
On its website, Coherent Logix lists 32 patents for ATSC 3.0 standards, with 16 filed in the US. We checked in with an Avanci Broadcast contact, who could not recall Coherent Logix, and wondered how one can withdraw from a pool when one was not a founding member. We are waiting for some further details from Coherent Logix on this matter, but the patents suggest that some sort of licensing agreement is going to have to be struck, or the lawyers shall be unleashed.
Coherent Logix popped up on Rethink’s radar recently, when it joined the Greening of Streaming initiative. Coherent Logix’s processor has a very low power design, and to cut a long story short, it can provide the same throughput for much smaller power consumption. To this end, both traffic routing and video compression are target applications, as well as a low-power WiFi 6E chip.
Starting with the latter, Coherent Logix has established a joint venture called AkiraNet, with two partners – Zinwell and SunPlus. The WiFi 6E chip will tape-out in Q3 this year, and Fabiano says it will be much cheaper than current rivals. He pointed to a $900 pair of WiFi 6E devices, and said the AkiraNet approach could be as low as $90, using powerline and an AI-based algorithm to best route traffic.
Thanks to the reprogrammability of the chip, it should also mean that any updates for WiFi 7 can be pushed to already-deployed devices. With its 3-watt power consumption, Fabiano notes that its wireless performance is close to that of the Ethernet connection, and a fraction of rival WiFi implementations – which can range between 10 and 20 watts. Notably, the architecture should ensure better low-power sleep functions too.
Fabiano said the design was close to a breakthrough with one of the big CPE players. “We have expended some effort there, and have spent time with some of the operators, but this has resulted in the operators informing their traditional vendors about the principals of the pitch – and not a sale. We are confident that we can beat the CPE vendors, once we have a foothold.”
The other target application is in the networking side of things. This is where the HyperX silicon architecture comes into play, which is billed as a processor ideally suited for edge applications.
Coherent Logix traces its origins back to a defense contract, where its founder, Michael Doerr, was struggling with the space and power usage of an FPGA. This led to the creation of the novel architecture, which – when it could not be disproved – saw a person leading the project inside the contractor help to launch the business.
This led to an outside investor coming in, and the company began pursuing military and aerospace work. It was found that the architecture was quite resistant to radiation events, which made it well suited for use in space – where rogue atomic particles can flip transistors and bork a regular computer.
Now on the fourth-generation design, Lockheed Martin is a big fan of the chips. To this end, Coherent Logix often does not know where its chips actually end up being deployed. A fleet of US government satellites is using them, it seems.
The new HyperX houses 416 processing cores, which are paired with four RISC-V CPU cores that coordinate the workloads. A smaller fifth control core handles the operating system functions.
The architecture is an asynchronous design, which has been built such that it does not require the interrupts of typical computing architecture. This allows it to use much less electricity, said Fabiano.
Coherent Logix has tested it against Intel and AMD FPGA designs. “We use around one-twelfth of the power, one-tenth of the space, at around one-fourteenth of the price, for a similarly performing radiation-hardened component. The real secret sauce is the toolset for the software developers,” said Fabiano.
This toolset includes a simulation environment, which allows developers to experiment with the chip without owning one. It enables live troubleshooting, as well as experimentation with the reprogrammable features of the design.
The business model for Coherent Logix is to design the chips, have them manufactured, and then sell the chips to end-customers. Some are direct buyers; others are integrators. On top of the chips, software and services are sold, and in some cases, a royalty is also collected if someone else manufactures the chip.
A notable feature is the sale of software-defined functions. “Instead of implementing a video codec in hardware, we can do that in software and then license those core software modules and libraries,” said Fabiano. This would apply for any software function, and would allow for software development partners to essentially have access to an app store of sorts.
Direct comparisons are always challenging, but Fabiano said that the Coherent Logix architecture performs equivalent to two geometry nodes smaller than its rivals. “Our 14nm is comparable to a 7nm, while outperforming it. Our upcoming 7nm design should outperform their 7nm by two orders of magnitude.”
“An Intel software-defined radio example had an FPGA that ran out of arithmetic cores at around 1.2% of the device capacity. That was a $17,000 unit, and ours could outperform it by around 6x, and cost around $4,500, with a 60% margin. In a more challenging environment, we have a comparison between a $130,000 Xilinx unit and a $24,000 design from us, which is 4x as capable,” said Fabiano.
Of course, defense contracts can easily stomach the difference in cost, as there are other integration costs to consider in eight and nine-figure deals. However, if the throughput claims stand up to scrutiny, it does suggest that the Coherent Logix silicon could knock lumps out of the likes of Intel and AMD in the networking server world, and the data center more broadly.