The dominance of a few processor makers in the mobile market ‘ Qualcomm in handsets, Freescale and Texas Instruments in base stations ‘ has made it difficult for their customers to differentiate their products, especially as the trend towards highly integrated SoCs (systems-on-chips) increases uniformity further. As manufacturers scrabble for market share in margin-squeezed segments, they are becoming more open to seizing the silicon initiative back from the chip giants and commissioning their own designs. This, in turn, provides an opportunity for semiconductor IP licensors to pursue a new customer base, among OEMs as well as processor makers.
This has been seen in the smartphone space, particularly at Apple. The iPhone maker led the way in creating its own processor, harnessing its own ARM technology licence. And though Qualcomm has dismissed the 64-bit capabilities of its latest version, the A7, as a ‘marketing gimmick’, nevertheless such launches prove that a device maker can actually leapfrog a specialized chip supplier and clearly differentiate its product from the pack. Others will not go as far as to design their own central processor, but may surround a Qualcomm Snapdragon with their own coprocessors and DSPs in order to create a unique experience.
The same trend is starting to creep into base stations, where OEMs face major challenges as the operators move towards LTE. They need to resist, for as long as possible, the commoditization of their products while they make the transition towards a network that is largely driven by software, and as carriers embrace new architectures such as HetNet (heterogeneous network) and Cloud-RAN, they need a platform which is adaptable to many cell sizes and form factors, from tiny metrocells to centralized baseband farms. In the quest to stand out from the crowd in the newest base station designs (see separate item), they are increasingly open to taking back control of their processors, rather than relying automatically on the SoCs of the major base station silicon suppliers.
Eran Brinman, VP of marketing at DSP (digital signal processor) IP licensor Ceva, commented: ‘Some OEMs design their SoCs now, or they define them in detail and then tell ASIC vendors what they require. Some invested a lot in software for a TI DSP but now they want an open system where they can reuse their software and architecture, but go to different ASIC vendors to keep them price competitive.’ The mindset shift, and the investment in skills and design, required to make this change are significant, not to mention leaving hundreds of man-years of TI software development behind. Brinman believes OEMs are being forced to take this step because the traditional architectures are not delivering the performance necessary for LTE-Advanced, or the flexibility that will be needed for HetNet.
The Chinese vendors are leading this charge for self-sufficiency. Huawei, of course, has its own chip operation, HiSilicon, and also customizes some of its third party platforms extensively. And in August, ZTE announced a licensing deal with Ceva – which aims to be to DSP cores what ARM is to mobile processor IP. ZTE licensed the Ceva-XC DSP core to underpin its own-designed base station SoC, targeting multimode TDD/FDD-LTE products mainly for its home market.
This was a breakthrough for Ceva, whose considerable licensing success has been mainly in mobile devices, as well as audio and imaging. It reflected the belief of some OEMs that they will achieve differentiation, and even better cost and supply chain control, if they develop their own ASICs (or at least to license cores in order to commission these from a partner), rather than buying complete ASSPs (application specific standard products).
The key driver of this change is the fragmentation of the LTE market. OEMs need to be very flexible to support many different combinations of spectrum bands, cell sizes, air interfaces and LTE-Advanced features such as carrier aggregation. These current and future options will be deployed at different times and across different network architectures by each carrier, even as the performance expected of the base station will rise dramatically to support LTE-A.
Flexibility, and early support for emerging standards, are ways for smaller base station makers to steal a march on Ericsson and Huawei. Fifth-ranked ZTE has been prominent in this respect, with its early-stage moves into software-defined BTS and multimode TDD/FDD-LTE. To continue to drive home this advantage against larger, sometimes more ponderous rivals, it has its own chip division with ASIC design capabilities, and plans to expand this to keep up with Huawei’s HiSilicon operation (the larger Chinese vendor has deals with Ceva and with its main DSP licensing rival, Tensilica).
Ceva plans to tempt OEMs with this flexibility mantra. In early 2012 it launched its ‘universal advanced communications engine’, or Ceva-XC4000 family of programmable cores, which are designed to enable developers to enable new standards rapidly. There have been three previous generations of this range, and they have sometimes been used in base stations, as at ZTE – but the latest product in the family, the XC4500, is its first to be created specifically for the wireless infrastructure space. It will target modem functions in base stations of all sizes, but also other wireless infrastructure applications such as backhaul, Wi-Fi offload and digital front end (remote radio head) segments.
Brinman thinks remote radio heads will become an important application as distributed networks and Cloud-RAN become commonplace. RRHs have generally used FPGA chips because there was not a DSP with the performance to cope with the key DPD (digital pre-distortion) function. Now Ceva has scored some design wins in DPD and expects more.
The company claims the XC4500 DSP core is “the world’s first vector floating point DSP specifically designed for advanced wireless infrastructure solutions’, and that it delivers LTE-A class performance with far less reliance on hardware acceleration than the established platforms of TI and Freescale. The new core contains various features specific to infrastructure, such as a dedicated instruction set architecture, multicore support, a fully cached architecture, and industry leading floating point performance of up to 40GFlops. Hardware acceleration for specialized tasks like turbocoding is enabled via Ceva’s Tightly Coupled Extensions (TCE).
Although Ceva has ‘low single-digit share’ in a sector dominated by TI and Freescale, the firm can see significant growth potential. The infrastructure space is attractive in terms of shipments potential because OEMs generally use a large number of similar DSP cores in symmetric multiprocessing designs (whereas handsets have fewer DSPs, and may source a range of different designs optimized for certain functions such as imaging). The high volumes expected once small cells hit the mainstream will also boost shipments and these new base station formats are luring unconventional players into the market, which may have less established ties with the incumbent SoC providers (Mindspeed, a specialist in small cell silicon after its acquisition of Picochip, is a Ceva licensee).
The company stresses its close cooperation with the giant of IP licensing in the mobile chip world, ARM. Modern platforms will rely on many different combinations of processors, including DSPs, DSPs and others, and these need to maintain cache coherency as well as supporting dynamic scheduling of tasks among the processors, to optimize performance and power efficiency. This is the challenge addressed byARM’s AMBA-4 ACE bus design, implemented in the XC4500, and its emerging successor, AMBA-5. Ceva is one of the group of partners working on AMBA-5, which may point to a future interest in the next frontier for wireless infrastructure, the cloud server ‘ after all, very few other platforms in this market would require 128 processors. TI has already announced implementations of its Keystone architecture for cloud servers and for specialized, high performance blade to offload intensive tasks from standard Intel servers.
Will this be a new opportunity for Ceva-based DSPs, or spell their demise? In the purest view of C-RAN, as sometimes outlined by Intel, the C-RAN becomes just an application of the wider cloud, with all the base station functions entirely implemented in software on commodity x86 servers. Brinman does see a future where everything is virtualized, but believes, predictably enough, that this will be a new opportunity for DSPs. ‘It won’t just be Intel. There’ll be DSP too, and ARM,’ he said. ‘Alongside the x86 processors, there will be application specific microservers with DSPs and accelerators for specialized tasks, and those can still be virtualized too.’
While Ceva is a close ally of ARM now, a year ago it was looking to acquire processor IP of its own, making a bid for ARM rival MIPS – which it lost to another licensor, graphics IP specialist Imagination Technologies. So the DSP firm may have a moment of ‘what might have been’ when it sees Imagination’s announcement of the first MIPS product under its auspices. While MIPS’ main successes have been in broadband and set-top box equipment, and it has made little impact on mobile, the P5600 32-bit core claims to have the power efficiency and small size to go up against ARM in mobile and embedded markets. The first in a new Series 5 ‘Warrior P-Class’ family, it can operate from 1GHz to 2GHz and claims to be 30% smaller than comparable CPU cores, with between 1.2 and two times the performance and support for up to six cores per cluster.
It remains to be seen whether Imagination’s position in handset GPUs ‘ where it competes head-on with ARM’s Mali design ‘ will be enough to pull MIPS along with it into a mobile space where it has made repeated futile efforts. The firm lists tablets and mobile phones, as well as set-top boxes and microservers, as targets, but in reality, ARM’s dominance in the mobile device space is assured and it is more likely that MIPS could give its parent a boost in some unfamiliar markets, especially as graphics become a central feature of a widening range of embedded and consumer products, well beyond handsets.
As more manufacturers look to specify their own SoCs, it will clearly benefit IP licensors to offer as many cores as possible. So both ARM and Imagination now have both a CPU and a GPU, while Ceva may have failed to gain its own CPU too, but is pushing a combined ARM/DSP platform heavily via its partnership with the UK firm. As well as Ceva, TI and ‘ more recently ‘ Freescale have also pushed the ARM/DSP combination for wireless infrastructure, though with their own designs in the latter area.
Reflecting on the general trend for licensors to cover several bases, ARM’s former CEO Warren East said last year: ‘A number of technology pieces are needed. And thinking holistically is vital to make things take off. Maybe we need to get involved at the technology level. But more important is to make standards happen.’ As ARM’s activities in the ‘internet of things’ space ramp up, some have suggested that the company might branch out from its digital heartland in microprocessors and microcontrollers, into areas such as mixed-signal, wireless, MEMS and other components of wireless sensor networks. Most providers here, such as Texas Instruments, have their own architectures, but volume economics may well dictate in future that a common platform is adopted so that ‘ as with CPU and DSP cores ‘ OEMs can design their own platforms while retaining a common software and standards base.
In this environment, a battle of the cores for telecoms infrastructure and devices will break out in many areas, not just the traditional CPU battleground. A total of seven IP licensors – Andes, ARM, Asocs, Cadence’s Xtensa unit, Ceva, Imagination/MIPS and Synopsys’ ARC ‘ announced new or upgraded communications cores at this week’s Linley Processor conference, for instance, indicating the heavy focus on this space as rising data traffic demands drive development of heavy duty networks.
For Imagination though, it has bought into the CPU race at the wrong time, as MIPS is facing a tough fight to survive at all. Probably its biggest supporter has been Broadcom, which uses ARM-based processors for mobile devices but MIPS in its home networking and broadband offerings. But this week, the chip vendor announced plans for an SoC based on a customized implementation of ARM’s new 64-bit architecture, targeting communications infrastructure. Broadcom and ARM are also working together on a new SoC architecture optimized for Network Function Virtualization (NFV).
The announcement signaled a move away from MIPS for a wide range of products in future. This looks like another nail in the MIPS coffin in the networking space. According to the Linley Group, seven of the eight top comms processor vendors have announced or deployed an ARM strategy (the other one being Intel). Broadcom, AMD, Cavium, Freescale and LSI are recent converts, lured by ARM’s move to a 64-bit architecture, which will roll out in commercial SoCs soon. Once that happens, there is probably a 5-10 year phase-out period for the other platforms.
It will take that long though, and ARM will still have to battle hard with Intel. Currently, the UK firm has a tiny share of the communications processor segment, which is dominated by PowerPC, followed by x86 and MIPS. And most defectors from PowerPC have only, so far, adopted ARM for specific, low power targets such as small cells.
However, designs like Broadcom’s new Armv8 processor will help to push this architecture beyond the metrocell, aiming at cloud servers, communications and storage systems. Broadcom also said it was working with carriers, the Linaro group and ETSI on a software environment for network virtualization which would support multiple SoC architectures and make it easier for OEMs to migrate from its current MIPS-based XLP processor to future ARM chips.
That, in turn, will start to squeeze PowerPC’s lead, as ARM’s big-ticket credentials are established. Freescale, for instance, converted to the ARM design just for small base stations last year, breaking its sole reliance on PowerPC. But at this week’s Linley event, it showed off a new SoC for communications equipment and said it had started to build ARM cores into all its communications processors. It unveiled the QorIQ LS1, an ARM processor optimized for gateways, and particularly those managing myriad devices in the internet of things. The LS1 majors on power efficiency rather than raw horsepower ‘ it runs on the Cortex-A7 core, which Freescale points out is more commonly associated with battery powered products like handsets. The combination makes the LS1 the most powerful processor requiring less than 3W of power, the firm claims.
The company insists ‘ as it did when it announced an ARM-based small cell strategy ‘ that it is not abandoning PowerPC, but will continue to develop both platforms, targeting them where they are best suited and tying the whole range together with its processor-neutral application-level architecture, Layerscape. The ability to mix and match different CPU, DSP or other cores would indeed be a source of differentiation for chip designers and OEMs, and so neutral or standardized software layers and interconnects hold out the promise of a Lego-style approach to design. But while the dominance of one or two uniform SoCs may be under threat, it is another big step for the industry to support a free-for-all of core combinations. ARM and Intel look set to prevail, and innovation will need to rely on flexibility in the functions that can be built around those platforms.