Only a few years ago, the idea of open source processors being credible for equipment as specialized and demanding as a mobile RAN or core would have seemed unrealistic for mass market commercial adoption. But the shake-up of the telco chip ecosystem by open networks such as Open RAN on one hand, and by the impact of US-Chinese tensions on the other, are putting open systems in the spotlight.
This was highlighted last month when 5G-on-a-chip start-up EdgeQ announced that two former Qualcomm leaders – former CEO Paul Jacobs and former CTO Matt Grob, both more recently co-founders of XCOM – had joined its advisory board. EdgeQ is one of a group of start-ups, focused on advanced applications like 5G and AI/ML, to be using the open source processor architecture RISC-V. It aims to target applications where AI and 5G are both in use, enabling the same chips to accelerate both workloads and so achieve efficiencies in power consumption, space and processing.
Applying open source architectures to specialist use cases like 5G baseband processing is cutting edge, but the shift of telecoms networks to white box routers and to RANs running on cloud infrastructure is expanding demand for processors that can hit aggressive cost and efficiency targets.
In late 2018, the Linux Foundation placed its seal of credibility on the idea of open source telecoms hardware, right down to chip level, when it took over hosting of the RISC-V activities. Mike Dolan, VP of strategic programs at the Foundation, said at the time: “The same collaboration model applies to the hardware in a system, just as it does to software components.”
Shortly afterwards, Wave Computing announced that it would offer the MIPS architecture, which it acquired following the break-up of former owner Imagination Technologies, as open source code with no royalties or proprietary licensing. Other open source chip projects – admittedly further from mainstream commercial products – include the FOSSi (Free and Open Source Silicon) Foundation, LibreCores and OpenCores.
The Linux Foundation also set up the CHIPS Alliance, which is designed to accelerate and encourage the adoption of open platforms by creating open building blocks for different target use cases. Its mission statement does not specifically mention RISC-V, but that is clearly its initial target platform, at least. The founders of CHIPS (which stands for Common Hardware for Interfaces, Processors and Systems) were RISC-V’s most prominent commercial adopter, Western Digital plus Google; and two other RISC-V chip designers, Esperanto Technologies (a start-up focused on AI chips), and SiFive. Currently, the organization has 25 corporate and university members, and has added Intel and Alibaba.
Last week, the CHIPS Alliance announced a new executive director, Rob Mains, whose career has included roles at Qualcomm, Oracle, Sun Microsystems and IBM. He said the Alliance is “creating a platform that different companies and members can contribute to … and bridge us to the next stage of innovation”.
Mains sees part of his role being to look beyond specific open source technologies, and create a holistic open ecosystem to support open processors like RISC-V. “There are a number of different areas where we can promote standards and examples,” he said, citing bus protocols such as the Advanced Interface Bus (AIB) first developed at Intel, and interfaces between chiplets such as Western Digital’s OpenXtend. Both these are now hosted by CHIPS and LF. Another area of interest is in Open PDK (process design kit) infrastructure – Google and Skywater recently showed off a prototype.
Mains’ particular interest lies in electronic design automation (EDA) tools, where he sees an opportunity to expand open source techniques. This could prove controversial for those embroiled in the USA’s hi-tech stand-off with China, since EDA is an area where the USA dominates the global industry, and has been able to use this position to cut Huawei off from some of its suppliers. Partly in response to the strength of US intellectual property in certain areas of the semiconductor industry, Chinese firms are showing a particularly strong interest in RISC-V and associated developments.
The CHIPS Alliance is focusing on processors and system-on-chip (SoC) designs suited to infrastructure elements including baseband units, switches or edge nodes. It will build on the existing open source instruction set and tools and work on pre-configured building blocks which will ease adoption for a variety of use cases. This would help to reduce the risk of fragmentation, which is the key downside of most open source efforts once they achieve scale, and which the RISC-V Alliance has been discussing openly in recent months.
Its remit is broader than that of the core RISC-V initiative, which works on the instruction sets, as it can look at other elements, and at expanding the reach of the architecture to new hardware categories as data centers and networks evolve with the increasing impact of, for instance, artificial intelligence (AI). Its objective is to make it easier for companies to implement RISC-V in processors for given target markets, by reducing the development effort and avoiding duplication of work.