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10 April 2019

5G and vRAN among the targets for Intel’s integrated “data-centric” platform

At February’s Mobile World Congress, a notable trend was for the major chip providers to be assembling end-to-end portfolios that would enable them to address the entire 5G network from switch-chips in the transport domain, to processors and FPGAs to support virtualized RAN and core, to base station and edge computing platforms. At that show, Intel launched a base station system-on-chip (SoC) and talked up a silicon family that it has been assembling for some years, through inhouse development and acquisitions like those of Altera and LSI Networking.

Last week, the chip giant held its own event, entitled the Data-centric Innovation Day, at which it showed off new Xeon processors, as well as the AgileX platform, which provides a flexible and high performance complement to Xeon by integrating FPGAs (field programmable gate arrays) with new generation memory and custom chips.

These combinations will target the next generation of network equipment and servers. CEO Bob Swan said the launch event marked Intel’s transition from being a PC-centric company to a data-centric company. He said Intel’s role was not to help companies “move, store and process data”, which is increasingly in the cloud data center, not the PC or other device. This has resulted in Intel’s “first truly data-centric portfolio of products”, he added.

“This data is creating what I call an innovation race across from the edge to the network to the cloud,” said Dan McNamara, general manager of the Programmable Solutions Group (PSG) at Intel. “We believe that we’re in the largest adoption phase for FPGAs in our history.”

Intel has been working to tie its central processors and the Altera FPGAs tightly together to support performance enhancements for platforms that require both kinds of silicon; and to mitigate the slowdown in Moore’s Law by combining several chips, with different capabilities, together.

Typically, these combinations are for servers that will support very demanding workloads such as virtualized RAN, artificial intelligence (AI). Processor-intensive tasks can be offloaded from the CPU to be performed by optimized, specialized chips – FPGAs, programmable chips which are heavily used in base stations and vRAN; graphical processor units (GPUs); and even more specialized units such as Google’s tensor processing units (TPUs) for neural networking.

For Intel, the FPGA has been its main investment outside the CPU, once it accepted that even the highest performance Xeon would not support very demanding applications like vRAN to the best efficiency. Rivals like Nvidia have been more focused on GPUs, especially for virtual reality and AI. With its eyes firmly on 5G networks, Intel was focusing on FPGA-based applications for that market, including digital signal processors (DSPs) based on the new AgileX family from the Altera division.

The event was not specifically about telecoms, of course, but 5G was often cited as a good example of an application for the integrated platform.

Intel announced over 40 variants of its 14nm-plus second generation scalable Xeon, known as Cascade Lake, claiming a 33% average performance improvement over the first generation models, called Skylake. However, Cascade Lake uses the same micro-architecture as its predecessor. The next new micro-architecture, at 10nm, will be the basis of the upcoming Ice Lake Xeon range, which should appear next year. Intel is expected to offer a system upgrade for Cascade Lake later this year, called Cooper Lake, which would be a response to AMD’s forthcoming shipment of its new, memory-heavy Epyc family.

To respond to attacks on its data center heartland from the ARM community, notably Marvell, and from AMD, Intel has added four more cores to Xeon without increasing the price, bringing price/performance closer to that of ARM.

More importantly for telecoms networks, Intel has versions of Cascade Lake optimized for specific workloads such as networking, vRAN and virtualization. And to drive its x86 architecture deeper into the carrier and enterprise network, Intel also announced the Xeon-D 1600, which uses between two and eight older Broadwell cores, to increase performance per watt, combined with four 10-Gbit Ethernet controllers. This combination is specifically targeted at base stations, routers and switches.

Intel also announced AgileX, a family of 10nm FPGAs, the first Intel has designed entirely itself since the Altera acquisition in 2015. Intel claims that AgileX will deliver 40% more performance or consume 40% less power than its predecessor, Stratix.

More significantly, it is the basis of a customizable collection of other chips. AgileX is a heterogeneous package of logic, memory and interfaces around the FPGA core (which includes a configurable DSP and an optional Arm SoC). It comes with heterogeneous 3D system-in-package (SiP) technology for “any-to-any integration” — the ability to integrate analog, memory, custom computing, custom I/O, and Intel eASIC device tiles into a single package with the FPGA fabric.  Intel’s Embedded Multi-die Interconnect Bridge (EMIB) is used to tie together the different chips within a single package.

This enables customized compute devices, said McNamara. He claimed: “This any-to-any integration is really a game changer. This is really delivering new levels of flexibility and customization to our customers.”

The AgileX can then be connected to a Xeon processor via a cache-coherent processor bus, called UltraPath Interconnect (UPI), allowing the FGPA and Xeon memories to share the same address space. This reflects how far Intel’s thinking has come from the days when it insisted Xeon could do virtually any task, without the need for help from FPGAs or GPUs. In this architecture, the FPGA is a true peer to the CPU, not just a coprocessor linked by a PCI-Express bus.

And Intel, after years of resisting, is even readying a discrete GPU, the Xe, while supporting third party offerings too – an ARM SoC as an option in AgileX, and the ability to connect custom chiplets (from Intel or others) too, using the tools acquired with eASIC last year. eASIC has defined a proprietary approach for creating a ‘structured ASIC’, which is far cheaper than a full ASIC (though less programmable). It involves taking a wafer with
pre-defined logic and memory, then customizing it with interconnects in just one or two mask layers. Structured ASICs provide a midway option between full ASICs and FPGAs and will be increasingly relevant in power-constrained, but also high performance applications including  IoT and 5G use cases.

Intel has talked about a Xeon/FPGA hybrid since acquiring Altera, but has not commercialized such a product. In fact, main FPGA rival Xilinx got there first when it announced its new Versal architecture last year. This includes general purpose processors with some programmable gates, while Intel’s new offering is not really a hybrid, but a tightly packaged set of separate FPGA and processor chips, with Xeon being attached to the platform by the processor bus, rather than fully integrated.

The combination of Xeon, Agilex and Optane is heavily geared to cloud platforms – Microsoft already uses Intel FPGAs as accelerators which can be programmed to support various Azure tasks, such as compression, encryption and search, on a flexible basis. But Intel sees 5G as a key opportunity for its new platforms so it was keen to talk about telecoms, as well as the edge.

It had some customer stories to support its view. Japanese cloud provider Rakuten made a stir at Mobile World Congress when it detailed a cloud-native architecture for its imminent deployment of its own 4G network. Intel FPGAs, integrated with Xeon processors, will help accelerate traffic processing. And on the edge computing side, another strong opportunity for FPGA/CPU combinations, NEC is using Intel chips for its facial recognition engine, NeoFace.

Matt Beal, Vodafone’s director of technology strategy and architecture, spoke at the event by video. “Network workload has always been the hardest thing to inject in a general purpose processor,” he said. The expects the new platform to increase automation and reliability, as well as scalability.

Initially, AgileX will be programmed with the existing Quartus tools, but later this year, Intel will roll out OneAPI, a high level abstraction layer with a set of libraries that will support the FPGAs and CPUs, and Intel’s upcoming GPU. Another sign of Intel’s growing willingness to drive open interfaces is its open sourcing of its CXL chiplet technology for a cache-coherent processor bus. This open processor bus will be commercially adopted by Intel from 2021, to replace UPI, though some of the technology is already present in the current technology.

But in another part of the platform, critics were concerned that Intel was trying to lock customers in by using a proprietary protocol, DDR-T, to link the new Optane memories to the Xeon and FPGA products. The firm may have to replace DDR-T with something open in time. An Optane executive admitted to EETimes that Intel “will have to make a hard decision at some point about opening up” DDR-T.

Intel hires former Qualcomm CFO:

Intel has hired Qualcomm’s CFO, George Davis, to take the same role as EVP and CFO of the larger company.

In his new role, Davis will oversee Intel’s global finance organization and investor relations, as well as its IT operations.

Davis is replacing Bob Swan, who was appointed as CEO in January after seven months as interim chief, following the sudden resignation of Brian Krzanich after a relationship with a colleague was found to breach company policy. Todd Underwood, VP of finance and director of corporate planning and reporting, had been the interim CFO.

Swan said the hiring of Davis “will help us execute our growth strategy in pursuit of the biggest data-driven market opportunity Intel has ever had”.

Qualcomm has appointed David Wise, SVP and treasurer, as interim CFO while they look for a replacement for Davis, who had held the post for six years.

Prior to working at Qualcomm, Davis was CFO of Applied Materials, at the same time that Swan served on the company’s board.

Intel’s increasing diversity has 5G in its sights:

The integrated FPGA and hybrid offerings will be important to Intel’s bid to have a major role in 5G networks, which represent a high performance, high growth opportunity among cloud-based systems, along with artificial intelligence and virtual reality.

The combined offerings will help to reassure operators who do not believe a Cloud-RAN is viable because its functions cannot be fully supported by general purpose processors. That will be important if Intel is to translate its FlexRAN reference platform into commercial products. FlexRAN provides a reference architecture for 5G NR and Cloud-RAN, and is being used for a large number of 5G testing activities with partners like Aricent and National Instruments, and with operators.

Over time, FPGAs and hybrids could enable Intel to support massive platforms which will host RANs in the cloud, as Amazon AWS seems poised to do in future via an alliance with Xilinx; but also, potentially, Microsoft Azure, which uses Intel FPGAs in its Brainwave platform for neural networking.

As well as servers, FPGAs are an important element of base stations. Intel has a base station platform built around its Xeon processor with accelerators optimized for signal processing. Prototypes based on FPGA chips were used in China Mobile’s huge C-RAN market trial, for instance. Altera signed a strategic collaboration with the China Mobile Research Institute (CMRI) in 2014, focused on the future needs of 5G with regards to virtualization and FPGAs.

At this year’s Mobile World Congress, Intel announced its first full base station platform,  Snow Ridge, a 10nm system-on-chip, which Ericsson and ZTE have already committed to use in their vRANs. Ericsson will combine Snow Ridge, which is specifically optimized for wireless access workloads, with its own custom silicon.

Sandra Rivera, general manager of Intel’s Network Platforms Group, said Snow Ridge was designed to “focus on high performance control plane processing and packet processing in a small footprint and a power-constrained envelope. This allows us to reach into these platforms and applications that historically we have not participated in.”

Also at MWC, Intel announced a new FPGA Programmable Acceleration Card, the N3000, designed to accelerate virtualized 5G workloads including those requiring very high throughput or low latency. It is targeted at RAN and core systems. Affirmed Networks, a provider of virtualized 4G and 5G cores, is using the N3000 in its 200Gbps server, which supports 4G/5G core, with the FPGAs focused on smart load balancing.

And Japan’s new MNO, Rakuten, is using a combination of Intel x86 processors and the N3000 in its new cloud-native 4G network. It uses the FPGA PAC as the distributed unit accelerator, offloading Layer 1 functions such as forward error correction and fronthaul transmission from the Xeon Scalable CPU.