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6 March 2020

After years of trying, Intel rises to the challenge of the base station SoC

As noted in this week’s Special Report, Intel and Marvell have benefited from Nokia’s shift away from its homegrown base station chip architecture, towards a system-on-chip (SoC) based on merchant products. Nokia’s high profile change of heart may have thrown the spotlight on the two chip providers’ latest 5G-related announcements, but it is not the only news. Both companies have been discussing the developments they would have unveiled at the cancelled Mobile World Congress, and these reflect a rapid pace of change in the mobile network chip space.

This change is driven, of course, by the migration of the macro RAN from proprietary platforms based on equipment vendors’ own ASICs (application specific integrated circuits), to basebands running as virtual network functions (VNFs) on cloud infrastructure and general purpose processors (GPP). As discussed elsewhere, these processors need to be integrated with various accelerators to support the same level of performance as in the proprietary ASIC-based architectures, especially when low latency is involved. But those accelerators can come from merchant providers too, as the macro base station starts to follow a trail towards common open infrastructure, originally blazed in the small cell sector.

Intel is claiming a full family of chips for 5G. There are:

  • the latest Xeon processors, to support cloud infrastructure for centralized units (CUs) in the disaggregated RAN
  • FPGAs and structured ASICs from its Altera and eASIC acquisitions to support acceleration and offload of demanding base station tasks
  • switch-chips, including upcoming products based on its acquisition of Barefoot Networks, which makes Ethernet switch-chips for programmable white box networks
  • the Atom P5900 base station SoC, which will particularly power Distributed Units (DUs) with demanding latency requirements

The P5900 is the most interesting. It has been a long journey for Intel to offer a full base station SoC, rather than just hoping that it will be possible, one day, to virtualize all the baseband functions efficiently on Xeon. Back in 2013, it talked about making a base station product based on Xeon plus some specialized coprocessors. At the time, it had launched Highland Forest , its third generation communications platform, which paired a Xeon E5-2600 v2 processor with the new Coleto Creek chipset. That was optimized for high end telco infrastructure, and designed to handle various tasks including “applications, control and data plane traffic and to some extent signal processing”, as Intel said at the time.

The lack of leading digital signal processing (DSP) – a technology Intel left behind when it sold Dialogic in 2006 – remained a significant hole in any attempt to penetrate base stations, until Intel bought Altera for its FPGA (field programmable gate array) technology, which is commonly used for accelerators for compute-intensive tasks such as DSP, dynamic spectrum sharing, AI analytics, encryption and others.

David Fraser, technical sales director for Intel’s EMEA service provider business, explained that the P5900 is a 10-nanometer SoC that integrates compute, connectivity and acceleration into the same package. Its uptake will be driven, he said, by MNOs’ need to push processing further to the edge of the network, and by RAN virtualization.

He said the SoC can achieve 3.4 times more throughput than a  software-based designs, adding: “Within the 5900 is an acceleration engine that enables the key functions that happen at that  base station node in the network to accelerate natively, and to partner with structured eASICs where required.” An example would be the acceleration of processing between centralized and distributed RAN units, by offloading the  conversion between fronthaul connectivity standards and enabling efficient CU/DU partitioning.

Intel also announced a structured ASIC, Diamond MESA, which has the same footprint as its FPGAs, allowing the two types of solution to be swapped in a design cycle. Intel said Diamond MESA might be applicable to vendors developing new types of radio for Open RAN and vRAN. These could benefit from FPGA programmability and flexibility but without the cost and power overheads – structured ASIC provides a middle way between the FPGA and the single-purpose, inflexible hardened ASIC.

Some vendors, such as Ericsson with its Nvidia partnership, are looking at using GPUs as accelerators while Intel is relying mainly on FPGAs and its structured ASIC products. An endorsement of the approach came from Rakuten Mobile’s CTO, Tareq Amin, who has deployed RAN virtual network functions from Altiostar on a commercial hardware stack based on Intel silicon. This was “not trivial” Amin told TMN, adding: “L1 requires ultra-low latency to manage the radio access signalling. The challenge to do so requires you to harden the OpenStack NFVi layer. Intel had to do a lot of work on the DPDK (data plane development kit) layer, and of course enable hardware acceleration through their FPGAs.”

Matt Beal, Vodafone’s director of technology strategy and architecture, made a similar point recently, saying: “Network workload has always been the hardest thing to inject in a general purpose processor.”

Intel has set itself the aggressive target of winning 40% of the 5G base station processor market by 2021 – which is not just about direct rivals, of which Marvell is the only significant one in base stations, but about luring vendors away from inhouse designs for as many models as possible. That will be tough, given that Huawei relies on its captive silicon unit, HiSilicon, for all its requirements. However, it has pulled the target forward a year from when it originally set it, in March 2019, when it said the 40% would be achieved in 2022.

That initial goal was announced when the P5900 was first unveiled, under the codename Snow Ridge, a year ago. It was part of a major event which Intel said marked its transition from a PC-centric to a data-centric company, in which telco networks were a significant target. At that event, Intel announced over 40 variants of its 14nm-plus second generation scalable Xeon, known as Cascade Lake, but a bigger breakthrough has been made with this year’s Xeon launches, formerly known as Ice Lake, which implement a brand new micro-architecture, at 10nm.

Already with Cascade Lake, there were variants optimized for specific workloads such as networking, vRAN and virtualization, as well as the first FPGAs designed within Intel since it acquired Altera, and the first Xeon/FPGA hybrid.