The rising complexity of 5G radios, as they evolve to support large numbers of different spectrum bands plus Massive MIMO antenna arrays, is putting RF transceiver chip providers in a strong position in the overall RAN component value chain. This has seen Analog Devices (ADI) sign a string of strategic alliances with radio unit and RAN processor suppliers, which promise to give it a pivotal role in the emerging open RAN ecosystem.
One of these is with Marvell, a long-standing partner which extended the relationship to 5G Massive MIMO late last year. Marvell is building a comprehensive 5G vRAN semiconductor platform for both open and integrated architectures and will work with ADI on 4G/5G radio solutions focused on high orders of MIMO.
They will leverage ADI’s next generation RF transceivers, which have programmable digital front end (DFE), combined with Marvell basebands. The latter use task-specific silicon to enable the most demanding tasks such as advanced beamforming and Layer 1 software that can support the O-RAN 7.2 split between RU and baseband. In O-RAN environments, the result will be badged the O-RU Octeon Fusion 95xx silicon.
The companies explained to EETimes that supporting the low power, size and cost requirements for 5G infrastructure will require the signal processing chains between RF and mixed-signal technology to be optimized, with new digital solutions for the baseband. This will be particularly important in dense 5G environments such as smart cities, and in open RAN environments, where costs need to be kept low to deliver the capacity and large numbers of sites required.
A feature of the partnership is that it looks to support the performance challenges of Massive MIMO with task-specific ASICs, rather than FPGAs (field programmable gate arrays) or even GPUs (graphical processing units), which are being used in some other platforms for acceleration.
Raj Singh, head of the processors business group at Marvell, explained the benefits to EETimes, saying: “The new O-RAN compliant mMIMO systems require a significant amount of L1 digital processing in the O-RU. Traditional approaches using FPGA technology result in large, bulky, high cost design. By using optimized silicon solutions, the cost, power and size of the O-RU can be optimized.”
He added: “With the introduction of the optimized O-RU Octeon Fusion 95xx silicon platform, we are able to replace a number of expensive, power-hungry FPGAs with optimized task-specific silicon. This allows for significantly sleeker design which is easier and less expensive to install. Additionally, since the unit consumes less power there is a much better TCO.”
ADI has other strategic partnerships in vRAN and O-RAN, including alliances with Intel and NEC, both announced in 2020. Intel, having acquired FPGA specialist Altera in 2015, is focusing heavily on this technology for acceleration. It will combine ADI’s RF transceiver technology with its own Arria 10 FPGAs to support 5G RUs, particularly those supporting open platforms such as O-RAN (though the offering also supports proprietary fronthaul links between the RU and DU if required).
“ADI and Intel are developing an O-RU reference design to enable commercialization of hardware and software. Systems integrators and operators can port their code onto open processors and perform integration testing between the O-DU (which hosts the upper PHY and Layer 2) and the O-RU (which contains the lower PHY and RF subsystem),” said Joe Barry, ADI’s VP of wireless communications, at the time of the announcement.
The partners say the combined offering will be pre-integrated and therefore will reduce the cost and time to develop an open RU, lowering barriers for smaller RAN suppliers to enter the market, especially in enterprise and small cell platforms.