Nvidia is the latest semiconductor company to announce a new processor combining AI and 5G functionality, and brings its huge weight in the AI landscape to bear behind a burgeoning trend.
Its announcement came complete with a set of big-name partners to help target specific applications or vertical sectors. The latter include general enterprise, healthcare, industrial IoT, managed edge compute services, and mobile infrastructure itself.
Nvidia’s move follows a string of developments and releases over the past year, bringing together AI and 5G. These have come from both major semiconductor companies and start-ups.
The GPU giant’s strategy is to recruit partners to fashion its 5G and AI package in methodical pursuit of different use cases. The AI-on-5G platform itself integrates Nvidia’s Aerial software development kit with its BlueField-2 A100, a card combining GPUs (graphical processing units) and DPUs (data processing units), including Nvidia’s ‘5T for 5G’ package. This is designed particularly to address the industrial use cases requiring high performance 5G RAN and AI algorithms in a platform optimized to manage precision manufacturing robots, automated guided vehicles (AGVs) and drones, as well as wireless cameras.
For this industrial sector, Nvidia is collaborating with 5G RAN software developers Wind River and Radisys. These vendors both plan to tailor Nvidia’s Aerial AI-on-5G for industrial 5G applications.
The chip provider also has an alliance with telecoms software company Mavenir, targeting a broad swather of enterprise applications, including Industrial IoT but also healthcare and other verticals including telecoms. Mavenir is developing two 5G vRAN systems around the Aerial SDK, and will target the network operator segment for public 5G and enterprise AI applications with private 5G.
With Fujitsu, Nvidia is working on a 5G Open RAN system, starting with a system for midband spectrum between 1 GHz and 6 GHz. Japan’s largest MNO, NTT Docomo, is already working with Fujitsu and Nvidia in its own evolution toward Open RAN in 5G.
“Fujitsu is committed to developing Open RAN solutions for global operators based on Nvidia’s Aerial AI-on-5G and its accelerated GPU and DPU solutions,” said Masaki Taniguchi, SVP and head of the mobile system business unit at Fujitsu. “Network operators, including NTT Docomo, are asking for hyper-converged and software-defined 5G vRAN systems to deliver innovative solutions to their customers.”
Google Cloud is another Nvidia partner and is focused on extending its Anthos application platform for cloud-based enterprise development to the network edge, targeting both public and private 5G edge deployments. This is looking towards enterprise IoT applications harnessing Google’s analytics capabilities around the network edge. In this capacity Anthos will support servers incorporating Nvidia GPUs.
As for Nvidia’s arch-rivals, they have their own efforts in the 5G/AI space.
Qualcomm has embedded neural processing algorithms focusing on client devices to enhance visual processing around cameras, security and gaming. The role of 5G here will lie in enabling the AI processes to be distributed between the cloud and client devices as a result of the increased data rates and in some cases lower latency, as John Smee, VP of engineering and head of 5G R&D for Qualcomm, has indicated. “We are seeing a transformation happening, with AI going from the cloud to being distributed, such as on the edge or IoT devices,” he said.
Intel is also in the game with a different slant, combining AI and 5G in a structured ASIC package called eASIC N5X, which is optimized for edge compute and was unveiled in November 2020. Intel had predicted there would be a demand for 5G edge compute applications incorporating upgradeable security, featuring machine learning for adaptability. This led to the choice of the structured ASIC, as a hybrid between traditional ASICs and FPGAs (field programmable gate arrays).
Modern ASICs often incorporate entire microprocessors and memory blocks including ROM and working RAM, as well as flash, but are customized for a specific task and cannot be upgraded in the field. They combine high performance with optimal power consumption and low unit cost for the target process, but with higher development cost and extra time to market, as well as inability to adapt to changing requirements.
FPGAs retain some of those advantages while achieving field upgradeability, but do cost considerably more per unit and consume more power because their logic is not dedicated to a given task and so have longer execution paths dissipating greater energy.
The structured ASIC, or eASIC by Intel’s terminology, lacks the field upgradeability of the FPGA and so is not suitable for systems that require adapting. But it does benefit from the shorter development time of the FPGA, by being built around a common base array to which dedicated logic, memory, I/O and transceivers are added to yield a hardwired package. The chip designers only need to customize the interconnect and can skip most other steps involved in ASIC design, focusing fully on the custom functionality.