At Xilinx’s developer conference, the FPGA developer announced a partnership with ARM that sees ARM’s Cortex-M CPU design be made freely available in Xilinx FPGA designs, without fees or royalties. As well as the launch of Xilinx’s ACAP products, outlined back in March, the FPGA world has seen Lattice Semiconductor update its network-edge focus, looking to entice embedded developers.
Field Programmable Gate Arrays (FPGAs) are essentially reprogrammable chips, which can be customized in the field to optimize them for a specific computation task. The gist of their value is that they provide flexibility, allowing a user to create a system that can outperform general-purpose processors, like CPUs or MCUs.
There are alternatives to FPGAs, chiefly ASICs, but these do not offer option to reprogram – although they often will outperform all other chips at that specific given task. As such, a developer has a chance of pushing new code to an FPGA, in order to change its function to suit a new task, whereas an ASIC adopter would be stuck with the current design.
Typically, these families of chips are being used in servers, housed in data centers, but there is a growing trend for their use in applications at the network edge, as can be seen in Lattice’s announcement. A highly-optimized design could enable very compelling applications, if it can be squeezed inside a device and provided with enough battery capacity to keep it running long enough to fit the business case. To this end, there are two very different initial focus areas for FPGAs in the IoT.
The goal for ARM, it seems, is to win over FPGA developers to the ARM way of life, letting them enjoy the benefits of an established coding ecosystem and the integration tools to let them drag-and-drop the cores into their Xilinx designs. In the low-power world, ARM is worried about the potential rise of the open source RISC-V architecture, which could unseat it, but it also has to keep tabs on MIPS, which is now owned by Wave Computing – an AI specialist.
ARM is promoting its 32-bit microcontrollers, the Cortex-M1 (an updated Cortex M-0) and the new Cortex-M3 – although Xilinx uses ARM Cortex-A and Cortex-R cores in some of its deigns. These are going to be available in Xilinx’s Artix, Spartan, and Zynq chips.
In those chips, the MCUs are acting as coordinators, linking together the different components in the complex designs to ensure that they run in sync. Because it’s essentially a separate processor, you can also run additional code functions on the MCU, which can help expand options for developers that might not want to burden the FPGA elements with it.
The ARM DesignStart program is key, which is ARM’s developer platform and portal that is geared towards custom chips and FPGAs. You can download blueprints for the free chips here, apparently. Notably, the first DesignStart developer boards use FPGAs from Xilinx’s arch-rival – Altera, bought by Intel for $16.7bn.
Intel was somewhat forced to buy into the FPGA space to protect its Network Interface Controller/Card (NIC) market, where FPGA-based designs were encroaching on Intel’s 60% share of the NIC market. Buying one half of the duopoly, Xilinx being the other, allowed Intel to undercut much of the concern – as companies like Napatech were showing what sort of network optimization performance was available using expansion cards housing FPGAs in servers.
To this end, Intel scored a win with Microsoft, where Altera FPGAs would be installed in every new Azure server. Not long after that announcement, Amazon’s AWS said much the same thing, but didn’t specify which vendor/s it would be using.
Xilinx’s other big piece of news was the Versal processors, the first six in its family of Adaptive Compute Acceleration Platforms (ACAP). Introduced at the developer event, the two units are based on TSMC’s 7nm FinFET production process, and will be available in 2H 2019, after some early access programs for key customers.
There are currently two variants – the Versal Prime and the Versal AI. In the latter, there are 5 different designs, while there are 9 variants of the Prime. When Xilinx outlined the ACAP plan, back in March, the first chip was called Everest. That name is not mentioned in the new launch materials.
Essentially, the ACAP SoCs dedicate more space to the additional components required to create a comprehensive chip, effectively shrinking the relative size of the FPGA. It’s a heterogenous approach that is becoming more prevalent, especially in the mobile world – where Qualcomm and Apple are adding coprocessors to their designs, and Intel throws more stuff at its Xeon wall, hoping that some of it will stick.
The new ACAP family is intended to really pile on the pressure for Intel, especially in applications that require real-time responsiveness and AI programs. The dedicated AI Engine hardware block aims to provide those features, although Xilinx is still remaining focused on the data center, as that’s its area of highest growth. These designs might find their way into edge applications.
That network-edge opportunity might belong to Lattice Semiconductor, a much smaller company than Xilinx ($1bn market cap to around $20bn), but one that has turned its attention to FPGA-enabled applications. Last week, it announced upgrades to its sensAI stack, claiming to provide the accuracy of CNNs on a flexible milliwatt-scale FPGA.
It’s a big claim, which was also flanked by new reference designs for human presence sensing and hand gesture recognition. The CNN Compact Accelerator IP, for the iCE40 UltraPlus FPGA, supports a range of 16-bit to 1-bit quantization, which will let developers adjust sliders for trading off between accuracy and power consumption (similar to floating-point calculation decisions).
Enhancements to the same CNN Accelerator for the ECP5 FPGA were announced, including a 2x increase in memory bandwidth that should be well received for smaller devices. The sensAI stack aims to power devices using between 1mW to 1W of power, and so is in a different league to Xilinx’s new products.
The goal is to win over developers looking to use these AI tools in always-on applications, such as voice or image recognition. There are two main developer kits – the iCE40 UltraPlus for mobile platforms, and the video-focused ECP5.
“Lattice’s low power, small size FPGAs and neural network IP cores and tools, will significantly accelerate adoption of artificial intelligence at the edge,” said Amit Vashi, Chief Operating Officer, Softnautics, a sensAI Design Services partner. “With our expertise in machine learning, we are proud to be working closely with Lattice to enable sensAI solution deployments as evident by our jointly developed vehicle classification demo using ECP5 FPGAs”.