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23 October 2019

ARM responds to open source challenge, allowing user-defined instructions

It is not just the network hardware and software that are opening up, sometimes painfully, after years of proprietary systems. Even at chip level, there are pressures to open up the architectures, with open source initiatives targeting processors (as with RISC-V) and even modems. This is prompting response from the semiconductor giants as they go through their own process of adapting to a cloud and 5G world.

Intel has started to work closely with some open initiatives and to drive its interfaces as standards in areas like chiplets. Xilinx has announced an open software development platform to make its FPGAs more deployable and interoperable with other vendors’ components.

Now ARM, at its recent TechCon conference, made its own significant concession to an open world, relaxing its control over its instruction set architecture (ISA) and allowing a larger number of licensees to add their own customized instructions to chips based on its core IP.

The change, which initially applies to the Cortex-M family of cores for microcontrollers, was announced by CEO Simon Segars. In the past, ARM has been focused on protecting consistency in its programming model to avoid fragmentation (and sometimes to respond to Intel’s claims of having the only fully unified platform).

Fragmentation is the biggest risk and trade-off that comes with openness at any layer from chips to applications, but its virtuous flip-side is flexibility – which is increasingly necessary at a time when microcontrollers will be used in a vast number of different products and workloads, with different requirements, especially as the IoT gathers scale. So ARM expects many of the custom instructions to be implemented to accelerate certain tasks, depending on the target application.

“We are, for the very first time, enabling people to add custom instructions into ARM CPUs,” Segars said. “We have never done that before — we are a company famed for standardization.” But he acknowledged, that while that standardization had ensured that software written for one ARM processor would run on any ARM chip, it does limit flexibility to optimize chips for particular applications. He said: “What we’ve seen with the evolution of workloads people want to run on their devices: there’s a flexibility with what people want to do with the chips. With customization of the processors, you can put that right into the design of the chip.”

Other IP licensing firms, such as Cadence’s Tensilica and even MIPs, have boasted of their flexibility and user-defined instruction sets, while the open source RISC-V ISA is highly user-configurable. That was bound to push ARM to open up its architecture to the broad base of its customers, not just that rarefied group that pays large sums for an architectural licence and can customize the cores.

The first Cortex-M core to support customizable instructions is the Cortex-M33 and future additions will also have this feature. ARM Fellow Peter Greenhalgh also indicated that the capability will be extended to the Cortex-R family of real time cores, and eventually, it may even be applied to the Cortex-A application processor designs. Adding customization to to Cortex-R would allow chips to accelerate the highly specialized calculations that often enable real time control.

ARM insisted that it has reworked its toolchain to support user-defined instructions without compromising reliability, consistency or verification. It has also made the new capability compatible with Arm TrustZone, which will monitor the custom instructions to protect security. It has taken some steps to guard against fragmentation. The new instructions will be interleaved with standard ARM instructions, and the company will encourage customers to use the custom additions mainly in called library functions. Licensees will not have to pay extra to deploy custom instructions.

The firm was clear that evolving Cortex-A in this direction would be complex and would not give a timescale, or even a firm commitment to do this at all, though it did promise larger numbers of its own instructions and extensions to provide customers with a longer menu of options. For instance, the next generation of Cortex-A cores after Hercules, codenamed Matterhorn, will feature new instructions to accelerate matrix multiplies, which could achieve a tenfold improvement in doing calculations commonly used in machine learning neural networks.

This clearly stops well short of the openness of RISC-V, but ARM’s dominance in the mobile processor space gives it significant leeway to evolve its model gradually before it is severely challenged by open alternatives, rather than taking the risk of opening up its flagship architecture too hastily and taking on board the downsides that may put many chip designers off an open approach – related to security, fragmentation and lack of consistent quality baselines.

This is the second step towards greater openness that ARM has announced in the space of three months, following the launch of its ARM Flexible Access program in July, which was designed to make it cheaper and easier for companies to get started with developing on ARM cores.

Under that scheme, customers pay only a “modest” upfront fee – $75,000 for entry level (one SoC tape-out per year) and $200,000 for standard level (unlimited tape-outs) – but receive the same support and maintenance services as full customers. They then negotiate licensing deals when they are close to the production phase of a new chip. This means they do not take the risk of paying for ARM technology in the early stages of the design, which they may end up not using in production. But they will be able to engage with ARM and its IP pre-commercially, and then pay just for what they end up using for full products. This should reduce the allure of open source or low cost alternatives, argues ARM, while maintaining the value of the IP once it has been adopted.

“By converging unlimited design access with no upfront licensing commitment, we are empowering existing partners and new market players to address new growth opportunities in IoT, machine learning, self-driving cars and 5G,” said Rene Haas, president of the intellectual property group at ARM.

Most processor cores within the Cortex-A, -R and -M families are included in the scheme, along with TrustZone and CryptoCell security IP, selected Mali graphics processors, and system IP.

This mechanism joins the standard licensing – which is likely still to be advantageous for large customers or those which are fully committed to the ARM architecture, since they will have less need to evaluate Cortex, and will be in a position to negotiate better deals over time. These customers will also have earlier access to the most advanced new ARM designs, and some licensees also have architectural partnerships, which enable them to customize the ARM cores to differentiate their designs further.

ARM also offers DesignStart, an even lower cost way to experiment with its architecture, though it comes with community support only. This is free for the Cortex-M0, M1 and M3 microcontroller cores and costs $75,000 for the Cortex-A5 processor core.

ARM told TechCon that it was also applying lessons from the open source world to its internal and partner environment, aiming to harness the best collaborative practices, without some of the risks. For instance, it has previously placed its IoT-focused Mbed OS in open source, and has now opened up the governance of that software platform to its silicon partners, allowing them to help to shape future evolution. Active partners in that program include Analog Devices, Cypress, Maxim Integrated, Nuvoton, NXP, Renesas, Realtek, Samsung, Silicon Labs and u-blox.

Also at TechCon, ARM announced yet another industry consortium focused on

autonomous vehicles, the AVCC, signing up Bosch, Continental, Denso, General Motors, Nvidia, NXP and Toyota as founding members. Initially, the group will develop a set of recommendations for a system architecture and a computing platform to promote scalable deployment of autonomous vehicles.