CES: ARM unveils latest safety critical core for auto market

With smartphone saturation a concern, and low power IoT devices inherently being  low margin products, ARM has turned its attention to all manner of other applications, as ways to grow its business. With a bit more freedom these days, thanks to new owner Softbank’s cash, the chip IP designer’s focus has shifted further towards the data center and automotive markets.

A new safety critical chip design was revealed, ahead of the Consumer Electronics Show (CES) this week. This is the latest addition to ARM’s Safety Ready family. The ‘Automotive Enhanced’ (AE) processor, the Cortex-A65AE, has been designed in a 7nm process, and is ARM’s first multithreaded processor core with the integrated safety features that will make it an option for automotive systems that have to meet stringent regulations.

The Cortex-A65AE is being aimed at two areas in the car – handling sensor data for autonomous systems, and running cockpit and in-vehicle infotainment (IVI) systems. Previously referred to as Helios-AE, in ARM’s roadmap discussions, the new chip uses ARM’s Split-Lock approach to provide the multithreaded processing capability.

The other AE chip in ARM’s portfolio, the Cortex-A76AE, which was unveiled back in September, also featured Split-Lock. The redundancy technology was more commonly found in ARM’s mission-critical 32-bit microcontrollers (MCUs), so its debut in a 64-bit architecture was notable. At the time, ARM said that Helios-AE and Hercules-AU were the next two designs, and so we now know that the Cortex-A65 variant is Helios-AE. There’s no hint about what Hercules-AE will feature.

At the time, the Cortex-A76AE was being billed as the ‘world’s first autonomous class processor,’ and with a 64-core configuration on the cards, it seems that this is being aimed at the heaviest lifting in the cars. By comparison, the Cortex-A65AE seems to have a pretty clear focus – handling multiple streams of data, whether they be from a sensing device like a camera or radar unit, or multiple video feeds and dashboard clusters.

ARM’s argument is that advanced cars will need to process a lot more data, to help them understand the world around them – via cameras, LiDAR, and radar. As such, they will need processors that can translate or shift the raw data pulled from these sensors into something that the main computer inside a car can understand, with the confidence that the data throughput will not be compromised by errors. ARM says that the new chip is perfect for this task.

While lower core-count Cortex-A76AE configurations could be used here, for the ’Perceive’ functions, the eight-core and upwards A76AE chips are what ARM envisions actually making decisions for these vehicles. In its diagrams, an 8-core A65AE is paired with a sensor, which then feeds its outputs to a four-core A65AE or A76AE, which in turn feeds data to the decision-making eight-core A76AE.

ARM has also poached former Intel executive Dipti Vachani, and has appointed her to lead the automotive and embedded wings as SVP and general manager. Vachani was previously Intel’s GM IoT.


Split-Lock is a system that allows a processor to function in two modes. The Split function means that two processor cores can work independently of each other. In Lock mode, the two cores are paired to run in lock-step, so that they perform the same tasks. This allows a system to spot a hardware-induced error, because the computation will differ, which then lets the main system know that something has gone wrong.

Should the monitoring system spot an error, identified through Split-Lock, then it can intervene – reverting to a last-known good configuration. The intervention system can be run on the SoC that houses the Split-Lock cores too, which should save on resources. There are arguments in favor of having that system running on physically separated hardware, but at that point, you’ve moved into a world where we have redundancy on redundancy – which quickly gets convoluted.

However, more conventional split-lock systems tend to use at least three cores in lock-step, so that there would be a clear ‘winner’ if one of the cores failed. That configuration would then let you know which core not to trust, so in the Cortex-A76AE, it would seem that you would want to be using at least four of the 16 cores to have that capability. After all, you won’t want to use a core which you now know to have some sort of hardware fault. ARM does say that two pairs of locked CPUs are available, but also believes that just the one will do.