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20 March 2019

Complex needs of comms and cloud infra drive open source activity

Only a few years ago, open source activity in telecoms networks was associated firmly with software. The idea of open source hardware, let alone chips, for equipment as specialized and demanding as a mobile RAN or core, seemed unrealistic for mass market commercial adoption. There was ‘open’ of course – a common design, like ARM’s or MIPS’ processor cores, which could be licensed by anyone, by contrast with Intel’s rarely-shared x86. But now, emerging network hardware platforms, including white boxes, lend themselves to an extension of that openness, reaching even into full open source communities.

Mike Dolan, VP of strategic programs at the Linux Foundation, commented on the change in a recent interview, saying: “The same collaboration model applies to the hardware in a system, just as it does to software components.”

The most prominent open source processor effort is RISC-V, established in 2010 and extending its reach into a wide range of designs, targeted at use cases from ultra-low power real time chips, to communications infrastructure. The RISC-V Alliance handed its developments to the Linux Foundation, which is becoming a massive powerhouse in telecoms networks, hosting a variety of initiatives including the Open RAN (ORAN) Alliance and ONAP (Open Network Automation Protocol), some under its LF Networking Fund umbrella.

RISC-V is not the only open source game in town any longer. In December, Wave Computing announced that it would offer the MIPS architecture, which it now owns following the break-up of former owner Imagination Technologies, as open source code with no royalties or proprietary licensing. Other open source chip projects – admittedly further from mainstream commercial products – include the FOSSi (Free and Open Source Silicon) Foundation, LibreCores and OpenCores.

Now the Linux Foundation has set up the CHIPS Alliance, which is designed to accelerate and encourage the adoption of open platforms by creating open building blocks for different target use cases.

Its mission statement does not specifically mention RISC-V, but that is clearly its initial target platform, at least. The founders of CHIPS (which stands for Common Hardware for Interfaces, Processors and Systems) are RISC-V’s most prominent commercial adopter, Western Digital plus Google; and two other RISC-V chip designers, Esperanto Technologies (a start-up focused on AI chips), and SiFive.

The CHIPS Alliance will focus on processors and system-on-chip (SoC) designs suited to infrastructure elements including baseband units, switches or edge nodes. It will build on the existing open source instruction set and tools and work on pre-configured building blocks which will ease adoption for a variety of use cases. This would help to reduce the risk of fragmentation, which is the key downside of most open source efforts once they achieve scale, and which the RISC-V Alliance has been discussing openly in recent months.

Its remit is broader than that of the core RISC-V initiative, which works on the instruction sets, as it can look at other elements, and at expanding the reach of the architecture to new hardware categories as data centers and networks evolve with the increasing impact of, for instance, artificial intelligence (AI). Its objective is to make it easier for companies to implement RISC-V in processors for given target markets, by reducing the development effort and avoiding duplication of work.

Zvonimir Bandic, senior director of next generation platforms architecture at Western Digital, said: “I do expect all the open standards organizations and all the different flavors of the open community to be very friendly to CHIPS Alliance. It’s just a different scope, but we can all work together at the chip level.”

Bandic explained that the RISC-V Alliance “does not specify the actual implementation of a RISC-V compute, so potential architectures range from small IoT devices to big data center processors. The best analogy would be the common Linux operating system for all the computers in data centers today, with every possible detail of source code known and documented.” With the new initiative, companies and individuals can contribute to common designs. “CHIPS is looking at commonalities with RISC-V based architecture so that companies can work together on the building blocks for products,” Bandic added. “Working with these common components and building blocks, we can have tremendous acceleration of innovation and significant cost reductions.”

He hinted that the new group could even look beyond RISC-V itself for some of its building blocks, saying: “Although it’s very much RISC-V friendly and oriented toward RISC-V projects, in principle it can focus on other elements as well, or other hardware.”

The new Alliance sees one of its key responsibilities as protecting adopters from the risks and uncertainties about the legal and patent protection processes which apply in an open source world. Bandic told FierceWireless: “There have not been enough efforts involving large companies and academic institutions due to unclear legal conditions and the challenges of hardware design tools constantly adding new IP. The CHIPS Alliance is meant to be an organization to resolve those problems and allow large entities to work together on open source hardware projects and share resources.”

Amir Salek, senior director of technical infrastructure at Google Cloud, said in a statement: “We are entering a new golden age of computer architecture highlighted by accelerators, rapid hardware development and open source architecture and implementations. Google is committed to fostering an open community of collaboration and innovation in both hardware and software.”

The CHIPS Alliance will follow similar governance practices as other Linux Foundation projects, with a board of directors, a technical steering committee and a community of contributors who will work together to manage the project.

Western Digital will contribute its nine-stage, dual issue, 32-bit SweRV Core, together with a test bench, and high-performance SweRV instruction set simulator. It will also contribute to the specification and early implementation of the CHIPS OmniXtend cache coherence protocol.

Google will contribute an instruction stream generator environment – based on the Universal Verification Methodology (UVM) – for RISC-V cores. This is used to verify architectural and micro-architectural corner cases of designs.

SiFive will contribute its RocketChip SoC generator, including the initial version of the TileLink coherent interconnect fabric.

On the same day that the new Alliance saw the light of day, Intel and a group of partners formed another consortium, which aims to develop open interconnect technology called Compute Express Link (CXL). This group does not conflict with the CHIPS Alliance – it is focused on a lower level, more specific requirement, and Google is common to both. Other founding members, apart from initiator Intel, are the cloud players (Facebook, Alibaba and Microsoft), plus cloud hardware providers Dell EMC, HPE and Huawei, and networking giant Cisco.

Jim Pappas, director of technology initiatives at Intel, said the CXL Consortium is “encourages any silicon provider to join and contribute to the development of the specification”, highlighting Intel’s increasing willingness to emerge from its x86 stronghold and drive open specifications that will help fill those gaps in its platform, with less cost and time than taking the ‘not invented here’ approach of old.

The interconnect technology will be important in compute-intensive platforms such as vRAN, and for applications like encryption and machine learning, which will require large numbers of accelerators (such as FPGAs, graphics processors and digital signal processors) to offload specialized and heavy duty tasks from the central processor (CPU). Pappas said: “Compute Express Link is a technology that exists between the CPU and accelerator — creating a high speed, low latency interconnect that removes the bottlenecks in computation-intensive workloads.”

Intel developed the technology and has donated it as the Consortium’s first release. Other members will then contribute to future releases. The first iteration will be available to Consortium members in the first half of 2019, and Intel itself plans to incorporate CXL in its Xeon processors, FPGAs, GPUs and SmartNICs from 2021.

Open Compute Project attracts new support:

One of the catalysts for confidence in open hardware platforms in data centers was the formation, in 2010, of Facebook’s Open Compute Project (OCP). This aimed to transform the economics of hyperscale cloud platforms by defining standard specifications that any service provider could mandate, and any server maker could adopt. Facebook then followed up with the Telecom Infra Project (TIP), which aims to do the same for the telecoms network, and has a wide range of projects focused on small cells, macro base stations, backhaul and vRAN interfaces.

The OCP, in many ways, has a simpler task than its younger cousin, because the cloud server is a more homogeneous platform than the network with its long chain of elements. But that is not to underplay the group’s achievement. At its Summit last week, Huawei said it would adopt the OCP’s OpenRack specs for all its public cloud platforms worldwide from 2019; while China’s cloud operator Baidu joined the group as a platinum member.

According to new research by IHS Markit, most OCP sales are still to its founding members, Facebook, Microsoft and Rackspace, but sales to non-board members are expected to have doubled between 2017 and 2018, outrunning forecasts to reach $2.56bn last year. By 2022, the researchers forecast non-board revenue will reach $10.7bn. The figures are still small as a percentage of the total market for data center hardware ($127bn in 2017), and there is little interest, for obvious reasons, from the big four providers – Dell, HPE, Lenovo and Cisco. Most OCP hardware comes from Taiwanese vendors such as Quanta Computer, Edgecore and Delta – companies which also see virtualized telecoms networks as a route into that space (see separate item). And Ericsson is also making OCP-compliant gear. And on the networking side of OCP, even Dell and HPE have certified products, while Cisco and Mellanox (now Nvidia) have open switches.


Can a RAN ever really run on general purpose CPUs? Chipmakers differ

In the run-up to MWC, ARM was adding new elements to its portfolio to flesh out an end-to-end offering for key telecoms markets such as 5G. In Barcelona, Marvell was the most impressive of the ARM partners in turning that full-platform potential into hard silicon, while Huawei and Samsung were both talking up the essential competitive edge that comes from full control of mobile network silicon.

Superficially, the message seems to go against the trend towards merchant chips and open platforms. But in reality, the infrastructure providers are increasingly using open designs for their inhouse silicon, and can integrate third party elements more easily from the market as a result. And while Huawei’s and Samsung’s homegrown efforts are a way to differentiate their own products, both firms have their semiconductor activities in standalone divisions, and get increasing amounts of revenue from the open chip market.

The willingness to use common platforms points to the need to keep the cost of developing complex systems under control, but also the increasing maturity of these solutions. ARM has not made a major dent on Intel’s server business as yet, but the adoption of its platform by Marvell and Huawei, for infrastructure, suggests that is starting to change. And from the adoption of a common design, perhaps it is a small step to an open source approach, as those solutions start to find their way into more challenging use cases, and more heavyweight suppliers.

Marvell was an early adopter of ARM’s server processor architecture, but when it acquired Cavium, it gained a more robust implementation. At MWC, the company announced a 5G platform, which combines elements of both companies’ product lines to support end-to-end solutions and nearly every aspect of the digital processing domain in 5G.

Raj Singh, general manager of the wireless business, is a firm believer that it will not be long before a general purpose processor architecture can handle most of the demands of 5G – base stations, small cells, edge nodes and vRANs, among other applications. In fact, he – and Marvell – are more bullish about this than Intel itself, which has been more willing to acknowledge the need for a heterogenous solution since it acquired FPGAs with the purchase of Altera.

Singh is right that early 5G New Radio (NR) equipment is heavily reliant on FPGAs (field programmable gate arrays) to support specialized workloads, but these have the trade-offs of relatively high cost and power consumption, and lower scalability than a fully integrated architecture with most of the work being shouldered by microprocessors, and with the necessary accelerators tied tightly into the platform. Marvell claims it is “leveraging decades of integration expertise with an unparalleled portfolio of baseband DSPs, ARM multicore SoCs, purpose-built hardware accelerators, Ethernet connectivity engines and system-level security solutions” to create a flexible and power-efficient platform.

Another key requirement for 5G, it argues, is that the system level architecture must be flexible to support the far wider range of use cases to which the new mobile network is expected to be applied, compared to 4G. Some will be application-specific, like fixed wireless, while others will need to support several levels of disaggregated RAN splits and core network virtualization.  Marvell claims its platform allows operators to develop systems for each use case quickly, without the need to implement expensive and inflexible ASICs (application specific integrated circuits).

“Marvell is uniquely empowering our network infrastructure customer base to accelerate their 5G systems via our highly integrated solutions,” said chief strategy officer Raghib Hussain. “Our 5G Ready portfolio is an order of magnitude better in terms of performance, power efficiency and overall implementation cost versus unoptimized field programmable pre-5G architectures.”

On the x86 side of the world, Intel used MWC to tout a deal with Ericsson for its recently announced base station platform, Snow Ridge. The Swedish vendor said it would use the new 10-nanometer SoC for virtualized 5G base stations from this year. This is not a complete solution though – Ericsson will combine Snow Ridge, which is specifically optimized for wireless access workloads, with its own custom silicon, rather than sourcing everything from the chip supplier. ZTE is also using Snow Ridge in its 5G vRAN products.

Sandra Rivera, general manager of Intel’s Network Platforms Group, said Snow Ridge was designed to “focus on high performance control plane processing and packet processing in a small footprint and a power-constrained envelope. This allows us to reach into these platforms and applications that historically we have not participated in.”

Filling in more gaps in its 5G line-up, Intel also announced a new FPGA Programmable Acceleration Card, the N3000, designed to accelerate virtualized 5G workloads including those requiring very high throughput or low latency. It is targeted at RAN and core systems. Affirmed Networks, a provider of virtualized 4G and 5G cores, is using the N3000 in its 200Gbps server, which supports 4G/5G core, with the FPGAs focused on smart load balancing.

And Japan’s new MNO, Rakuten – the star of the show in Barcelona this year – is using a combination of Intel x86 processors and the N3000 in its new cloud-native 4G network. It uses the FPGA PAC as the distributed unit accelerator, offloading Layer 1 functions such as forward error correction and fronthaul transmission from the Xeon Scalable CPU.

Intel also previewed a forthcoming new Xeon Scalable processor, codenamed Hewitt Lake, a highly integrated SoC designed for edge computing and distributed security. And the company unveiled its Open Network Edge Services Software (OpenNESS) toolkit, an open source reference guide to help cloud and IoT developers work more effectively with 5G and edge equipment providers, by simplifying network complexity for those developers.

Samsung is still taking the old-fashioned view that tough workloads such as vRAN require the full optimization of an ASIC, and that is also important to differentiate a base station vendor’s offering. The Korean company has its own technology deep in its 5G solution, which includes base stations and RF front ends, including for the millimeter wave bands in which Samsung has gained some clear leadership.

Alok Shah – VP of strategy, business development and marketing for the networks division of Samsung Electronics America – said in an interview at MWC that ASICs are crucial to allow the vendor to achieve the maximum reduction in size, weight and power – about 25% less than with a processor, he claimed, because all the discrete elements are put into the task-specific ASIC format.

“We really feel like being able to commercialize from the chipsets to the mobile devices to the infrastructure, we have a structural advantage that allows us to stay in front when it comes to 5G,” said Shah.



Marvell’s 5G NR Platform includes:

  • The Octeon Fusion-M line of RAN system-on-chip products, programmable with a 3GPP protocol stack split and Massive MIMO capabilities.
  • Multicore Octeon-based transport and packet core processors. The current generations power the transport layer supporting over 10m base stations today, says Marvell. It says its scalable data plane acceleration makes its embedded processors suited to 5G and 4G cores implemented in the heart of the network too, moving to a unified architecture for both transport and packet core.
  • For Ethernet networking, Marvell offers Ethernet switches and physical layer devices. The Prestera switches support hierarchical traffic management for mobile infrastructure, as well as advanced flow identification and access control for user-level security.
  • The company also offers 8×8 and 4×4 WiFi 6 solutions, the latest in a carrier WiFi range that also includes 802.11ax chips with Multiuser MIMO and OFDMA uplink and downlink, plus beamforming and integrated Bluetooth 5.
  • ThunderX2 is Marvell’s ARM-based server line, with variants optimized for vRAN and NFV workloads, and to support the migration of core functions like PDCP as they migrate into the cloud.