Processor designers are starting to sound like architects of buildings, not chips. For lovers of modern architecture, minimalism and invisibility have been important and radical trends of the past 30 years. Both these words are now heard with reference to processor IP, and their supporters are looking to do something equally radical involving – like the new-style buildings – new approaches to materials, processes and efficiency.
All this new thinking is, inevitably, being driven by the emergence of the ‘internet of things’ – the need for processors which have to meet a seemingly impossible set of demands. They need to be cheap, and therefore capable of huge volumes, yet they will be targeting thousands of different device types and use cases, with different requirements. They need to be ultra-small and ultra-low power, but still to pack in several connectivity options, some intelligence, various sensors and strong security.
The challenge is daunting, but it is spurring innovation among the processor designers, and should spawn some new approaches and even some new powerhouses. Invisibility is the new motto adopted by ARM, which held its TechCon conference last week, with its primary focus firmly on the middle ground between smart devices with full processors and OSs, and traditional dumb M2M gadgets. Its highlights were its souped-up MCU, Cortex-M7, and its new embedded operating system, mBed OS.
Minimalism, meanwhile, is the watchword of Cortus, a company which is eyeing ARM from across the Channel in France, and hopes to steal some of its thunder in the IoT.
These companies are David and Goliath in processor IP terms, but they both recognize that it will not be enough to shoehorn existing processors and controllers to meet the diverse needs of the IoT. New thinking will be required to hit the economics and the particular functionality that is needed, while being able to develop a relatively generic platform suited to so many applications, some of them as-yet undiscovered. And they will certainly not be alone. Imagination Technologies, ARM’s great UK rival in graphics processor cores, is harnessing its MIPS acquisition to offer integrated designs for wearables processors and other IoT markets. And of course there is Intel, with its Quark processor and its grand ambitions for its embedded unit and its important Wind River subsidiary.
Among these giants, Cortus is pinning its hopes on there being a wider range of architectures and suppliers in the IoT than there is in mobile devices. Most IoT products will have certain common features – support for sensors, various short-range connectivity options, and some processing, all highly integrated on the system-on-chip (SoC). However, VP of sales and marketing Roddy Urquhart thinks there will be less need for standardization, and designs will be optimized for different purposes, allowing different architectures to emerge with different key strengths.
He also sees the rules of competition shifting in the manufacturing process. The priority in mobile devices has been to drive down the geometries (Intel is pushing to 10nm), because the designs were mainly digital. “In the new wave of connected devices, designs will be based on mixed-signal and sensors-on-chip,” he said – a trend which will certainly create a more crowded and varied ecosystem for the IoT, drawing in analog and mixed-signal players like Texas Instruments and the M2M activities of Infineon, ST and others. That shift also “means coarser nodes, so there will be another area of discontinuity with the mobile wave, in manufacturing technology,” Urquhart told Wireless Watch. And where there is discontinuity, there is the chance for smaller players to steal share.
Cortus is highlighting two particular strengths, security and a flexible approach to licensees, to differentiate itself and its minimalist architecture. The 10-year old company traditionally competes with the ARM Cortex M0 microcontroller platform and has 38 licensees for its ultra-small 32-bit processor cores for embedded devices. Now it has announced a new instruction set, and two ‘v2’ cores, the APS23 and APS25, targeted at intelligent gadgets which are connected to one another and/or the internet, and need extremely low power coupled with high levels of security. Cortus supports the familiar model of licensing fees plus royalties.
The new chips use some of the proven technologies from the existing v1 family, which will still be marketed, but the v2 instruction set has about 16% greater code density to address the demanding power and size requirements of the IoT. This density helps address one of the trade-offs of the more complex firmware in modern architectures – increased instruction memory size, which increases power consumption. That has become as much of a concern as keeping the core size small, said Urquhart, and an important differentiator of v2 cores is that they need a significantly smaller instruction memory than v1. The continuing challenge will be to retain that advantage, but without letting the dense code slow down the core.
Therefore, another important claim is for silicon efficiency to reduce cost and power – the minimalist designs start at 10K gates for the APS23 and 20K gates for the APS25, compared to 12K and 30K for similar ARM designs, said Urquhart. Not that the firm will always be competing with ARM – sometimes an SoC designer might use cores from both suppliers in one platform, along with the rising number of other processors that mobile and embedded devices will include (a touchscreen processor in a smartwatch, perhaps).
The APS23 is the simpler product and targets always on/always listening subsystems and simple embedded systems, typically sporting connectivity options with lower clock frequencies such as Bluetooth Low Energy.
The APS25 core is aimed at embedded systems that need more computational performance and system complexity, or a higher clock frequency to support WiFi, for instance. It can support multicore designs and an interface for various coprocessors to handle demanding tasks. Up to eight coprocessors can be added to accelerate specific operations in hardware, and dual or quad-core SoCs can be supported. Cortus sees the crossover point between its two platforms being about 64Kbytes of code memory.
The coprocessor interface, and various security mechanisms, are important differentiators from ARM and Imagination’s MIPS. ARM has so far resisted offering a coprocessor interface. It does, of course, have significant security credentials, and is building a broad platform and de facto standards around its TrustZone platform. But there are specific features which Cortus has built into the APS25, in particular, which add extra security. One unique one is the Check architecture option, which allows the APS25 to be deployed as a Master CPU and a Check CPU, with both executing the same code in lockstep, triggering an alarm if the results don’t match. Alternatively, one can run the secure software while another runs application code separately.
In addition, Urquhart also says licensees are often attracted by the greater flexibility of Cortus’s licensing terms, which allow customers the ability to add their own “secret sauce”, under approval, to the cores, especially in the security area where the company has several specific licensees. The coprocessor interface allows customers to add and design specific algorithms while giving them full access to CPU registers. One such user is BlackBerry’s Certicom security unit, which used Cortus’s extendible instruction set to couple a security mechanism tightly with a CPU.
Other public Cortus v1 designs include a WiFi chip from Atmel’s Newport Media arm; touchscreen controllers from Point Chips, Imagis and LeadingUI; automotive sensors from e2v, Microsemi and NextChip; image sensors from Pyxalis; smartcards from StarChip; and security from Discretix.
This rollcall indicates how many processor core providers may fly well under the radar compared to ARM and Imagination, but can still carve out strong niches – niches such as auto sensors which may grow significantly in size in the IoT era when every embedded device becomes connected, to other devices if not the internet. Another example is Andes Technology of Taiwan, which sells cores for embedded applications such as GPS controllers and touchscreen controllers, but is moving into the IoT mainstream by targeting products like sensor hubs. The areas of expertise which have powered such companies in their niches, such as what Cortus calls minimalism, are set to become far more widely applicable, and even the giants may have to race to catch up with the specialists.
So what of invisibility, logically a next step from minimalism? ARM CEO Simon Segars mooted the idea in his keynote address at TechCon (see Wireless Watch October 2 for TechCon write-up). He said that the challenge for the IoT would be to shrink the size of silicon, while increasing performance, complexity and connectivity – and to keep all that invisible to the device user. “We should take it upon ourselves to make sure that we continue to do a great job of hiding away the complexity, hiding these components and what they do… so we continue to get a great adoption rate,” he said.
Applied Micro puts another nail in PowerPC’s coffin:
Another nail in the coffin of PowerPC – Applied Micro, the second largest supplier of PowerPC-based chips after Freescale, is to move all its products to the ARM platform by 2018.
The signs are not good for the venerable architecture. Freescale has introduced ARM into a growing number of its ranges (though it remains obstinately loyal to PowerPC in many network processors), and other suppliers have also jumped ship or adopted hybrid approaches. And it is a long time since PowerPC won a new convert.
The Applied Micro move is far more than symbolic for ARM as it will also take the UK firm into a market it has hardly tapped, for single-board computers (SBCs). Applied’s flagship ARM-based product will be a 64-bit multicore design for this segment, with four-channel memory support.
Single-board computers are dominated by PowerPC and x86 so Applied’s defection highlights once again the importance of ARM’s move to 64-bit, which is enabling it to chase these higher performance architectures in markets that were once closed to it, such as servers.
The new Applied device will be part of the HeliX family, which uses the X-Gene microarchitecture for small servers. The ARM-based SBC chip will be a 28nm chip due to sample in 2016. Applied is already planning X-Gene 3 devices to be made on a 16nm FinFET process with 8-16 cores on a chip.