Intel has been beefing up its network infrastructure efforts over the past couple of years, buying companies which will help it push into a wide range of elements from switch-chips (Fulcrum) to mobile network SoCs (Mindspeed’s Picochip unit and Avago’s Axxia). It aims to take on incumbents like Cavium and Freescale directly, as well as taking advantage of the trend towards virtualizing aspects of carrier networks, clearly a huge opportunity for x86-based platforms.
However, the attack on the carrier network may involve Intel making some architecture compromises, and even, perhaps, sneaking ARM into its portfolio – as the other x86 chip vendor, AMD, has already done more explicitly. Indeed, AMD was showing off its biggest ARM-based offering to date, Hierofalcon, at the processor IP giant’s TechCon conference last week.
One of the notable aspects of Intel’s Mindspeed and Axxia deals was that these companies’ offerings are ARM-based. Axxia, under its former parent LSI, had been a very close partner of the Intel arch-rival in the development of its 64-bit, multicore communications processors designs and its CoreLink technology.
On the device side, we have seen Intel persuading new partners like Spreadtrum and Rockchip of China to include an x86-based second string in their handset SoC portfolios – in return for significant investment and other support (see separate item). This would be a far bigger ask in infrastructure, but a reverse situation could be envisaged, especially in the virtualized RAN environment.
There, the vision is to run most of the functions of the base stations as applications on a centralized server, probably in the cloud (as trialled by China Mobile and Telefonica). That platform, in the Intel world view, would clearly run on large numbers of x86 processors, but it would still require specialized accelerators and other elements for particular functions, as well as stripped-down cell site units. In those areas, Intel might well accept some ARM processors, as well as tapping into its new acquisitions’ years of investment in technologies like DSPs, in which the chip giant has never excelled.
This would not be incompatible with a more flexible view of architectures, ushered in by CEO Brian Krzanich as part of his quest to push Intel into new markets. In order to get a starring role for x86 in telco networks, some uncomfortable supporting players may have to be tolerated. Intel has also been working hard on developing its own specialized coprocessors, optimized for specific network or data center functions, to run with its main platforms.
Its most recent push into telecoms networks came with the release of Sunrise Trail, a server reference platform which follows the earlier launch of the switch reference design, Seacliff Trail, part of Intel’s Open Network Platform (ONP) for switches in an SDN (software defined network) environment. The combination of x86-based switches and servers would be sufficient to replace 90% of the single-function hardware in many telco networks, argue fans of SDN and the related virtualization approach.
The ONP twins Intel’s components and packet-processing software with industry standard software stacks, such as the Fedora 20 operating system and VMM (virtual machine manager); the Hydrogen SDN controller from the OpenDaylight initiative; and the OpenStack-based orchestrator, Icehouse. The new design runs on Intel’s new Xeon E5-2600 v3 processor with its 89xx south bridge, and XL710 40G Ethernet controller.
The move to full SDN and virtualization will be a gradual one, and speed of progress will vary greatly between different parts of the network (RAN, in general, coming far behind packet core and CPE initiatives, for instance). However, some major operators are already conducting significant trials of various aspects of SDN and NFV (network functions virtualization), using x86 platforms, notably AT&T, Verizon, China Mobile, NTT, SK Telecom and Telefonica.
Some of them intend to start field deployments as early as next year so it is important for Intel to position itself as early as possible for the start of what promises to be a decade-long transition. Its vision, as articulated by the head of its communications infrastructure business, Rose Schooler, is to “transform wireless access into an intelligent, flexible network based on standard building blocks to fuel innovation and increase network efficiencies”. That will mean running application, control, data and signal processing all on a common architecture to reduce cost, improve flexibility, and support evolution to SDN over time.
Of course, the more established infrastructure chipmakers are moving towards SDN too, with their ARM and PowerPC platforms and their generally lower-cost, lower-power starting points. Broadcom’s XLP and Cavium’s Octeon are the big guns, and AMD has been diversifying its telco chip line-up and adding ARM processors to its mix.
At TechCon, AMD showed off the Hierofalcon CPU system-on-chip which it announced a year ago. This fits into its R-Series of high performance embedded designs, targeting applications like network and storage processors. It is the first ARM-based design to find its way into that range, where it will live alongside the x86-based ‘Bald Eagle’ CPU/APU. It is particularly aimed at virtualized network functions, an area where AMD believes the ARM architecture has advantages over Intel’s.
Scott Aylor, general manager of the embedded systems division at AMD, told The Register that ARM cores can be coupled tightly to network interface controllers in silicon, which optimizes NFV performance and reduces power consumption and package size. He also said he was seeing considerable developer interest and overall momentum behind 64-bit ARM, despite the greater installed bases of MIPS and PowerPC in networking gear of various kinds.
Based on 4-8 64-bit ARM Cortex-A57 cores, Hierofalcon supports the NFV specifications and, at TechCon, was demonstrated running a virtualized evolved packet core (vEPC). The demo harnessed an embedded Linux-based NFV solution and showed a mobile packet core running subscriber calls from simulated devices, with the Hierofalcon SoC hosting three key control and data plane functions – serving gateway (SGW), packet data network gateway (PGW), and mobility management entity (MME).
Other functions which have been virtualized on Hierofalcon, according to its vendor, include the content delivery network (CDN) and Dynamic Host Configuration Protocol (DHCP) server, which is used to assign IP, DNS and router addressed to connected devices.
Vodafone was one of the companies endorsing AMD’s demonstration and its multiplatform approach. “By leveraging ARM and x86 architectures and NFV, AMD is moving beyond just enabling enterprise and data center solutions, to the communications backbone where service providers need cost reduction and increased bandwidth,” said Adrian Neal, technology leader at Vodafone Group Services.