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17 May 2022

Xilinx goes “80% ASIC” with an RF chip for Evenstar Open RAN networks 

Even before it was acquired by AMD in a $49bn deal earlier this year, Xilinx had proclaimed that it was “no longer an FPGA company”. Not only did it have other product lines, notably in RF, but it had developed a flexible architecture that took in different kinds of chip, alongside the field programmable gate arrays (FPGAs) it had pioneered. 

 

Now part of a larger company that made its fortune in central processors (CPUs), AMD, Xilinx has an even more multi-faceted story for its markets, including one of its key targets, 5G infrastructure. Last week it unveiled its latest radio chip, the Zynq UltraScale+, which takes it several steps away from an FPGA-only platform. This is an RF system-on-chip (RFSoC) for the digital front end, an increasingly important component of the 5G radio unit because of the wide range of spectrum bands that need to be accommodated. 

 

Importantly, the SoC has been selected to be part of the Telecom Infra Project (TIP) Evenstar project, which is backed by Meta. This is developing open radio unit (RU) reference designs for Open RAN, in the hope of lowering barriers for smaller vendors to design such equipment, encouraging development of cost-effective and even commoditized units, which in turn will drive down the cost of deploying 4G or 5G.  

 

Xilinx also says its new chip is going into a north American production 5G network, and that may well be more lucrative than its Evenstar engagement, given the emphasis of that project on low cost networks. However, Evenstar is important for Xilinx’s credibility as an open platform, and for its parent AMD’s push to be a player in a vRAN/Open RAN market that threatens to be monopolized by Intel and Qualcomm.  

 

If the Open RAN vision is to be achieved, it will be important to be able to embrace and integrate multiple technologies, and multiple vendors, right down to semiconductor level. That will make it easier for the right combination of chips to be adopted for each price point, form factor and performance requirement, without sacrificing open and consistent frameworks.  

 

AMD, like arch-rival Intel and others, has recognized that one kind of chip can no longer hope to support all the different and demanding processes of a platform like 5G vRAN. Instead a combination is required – programmable chips such as FPGAs, for applications that need to be adjusted frequently; CPUs and graphics processors for scale and to support a wide range of applications; application-specific integrated circuits (ASICs) for optimized performance for one process. 

 

Xilinx’s new radio chip is “80% ASIC”, says the company, but combines the best elements of FPGA and ASIC components. Gilles Garcia, senior director at the AMD data center and communications group, explained that the mixture was balance to “achieve the most efficient use of spectrum with the lowest possible power”.  

 

The heavy use of ASIC should reduce power consumption and single-purpose chips have been used to optimize the interworking of the DFE with another key element of an RU, the power amplifier. The standards are sufficiently stable now to allow for the use of ASICs, whereas greater flexibility is required in the early stages of a technology, when changes are being made constantly.  

 

However, keeping some programmability through FPGAs provides more flexibility than an ASIC-only solution can offer, since Xilinx (and Evenstar) will need to target many vendors with different requirements, and using different combinations of spectrum bands. “Big Tier 1s will continue to do ASICs, but there are so many different flavors of radio that one size cannot fit all,” Garcia said.  

 

The new RFSoC could be used in traditional RANs but Xilinx sees vRAN and Open RAN as the best growth opportunities. Xilinx is the only standalone RFSoC DFE supplier that has been announced as part of Evenstar, most of whose members are RU equipment vendors and some operators (notably Vodafone, Deutsche Telekom and Bharti Airtel). Garcia says the Xilinx 4T4R RFSoC is the only one currently being used in Evenstar radios and that Fujitsu, Mavenir, MTI and STL are among those designing RUs to conform to the project’s specs. 

 

Such projects will be important for pooling resources in developing an open RU that could compete effectively with the proprietary base station RF platforms of Ericsson, or the market weight of Qualcomm has it starts to apply its smartphone processors and RF front ends to Open RAN infrastructure. 

 

Garcia says the Evenstar project is very close to one of its key targets, an RU priced below $1,000, or about 15% of the typical price of a 4G/5G radio. That does not mean a product based on Evenstar reference designs would be equivalent to, say, an Ericsson RU, but that it will offer a simple and cost-effective alternative for networks in which the Ericsson product would be overkill, such as those in rural areas or some enterprise scenarios. Without new sources of equipment, such networks will never get built because they could not be cost-justified. For instance, by contrast with high end Massive MIMO kit, the Evenstar reference design comes in a 4T4R configuration. 

 

“We are excited to see AMD’s RFSoC solutions incorporated into Evenstar RUs in collaboration with our ecosystem partners,” said Jaydeep Ranade, director of wireless engineering for Meta Connectivity. “As we continue to champion open, disaggregated solutions for the industry, we look forward to unlocking new ways to accelerate the pace of innovation as networks evolve.”