Toshiba says that it may have come up with a new approach to increase the storage capabilities in NAND flash memory by a factor of ten. The technique relies on creating new three dimensional arrays of flash, but it uses existing process technology, so potentially it could be adopted very rapidly with no increase in the chip die size. Toshiba announced the idea at a VLSI symposium this week.
In the new structure, pillars of stacked memory elements pass vertically through multi-stacked layers of electrode material and use shared peripheral circuits. Toshiba says that it is based on existing stacking processes, with some amendments whereby it etches holes down through the substrate, and then fills in these holes with pillars of doped silicon that form NAND cells (see diagram in pdf version).
NAND flash works on batch processes, and is made with cells connected in series. Toshiba’s array means the number of connected elements increases in direct proportion to stack height and it gives the example that a 32-layer stack would create a chip with 10 times the integration. Toshiba says this is just one approach that it is considering and it gave no indication of when chips made this way might appear on the market, but if everything it says is true, it could be under a year.
An increase of that magnitude would take chips from being able to hold around 8Gbits each today to more like 80 Gigabits, and might lead to devices like cellphones holding around 80 to 100 Gigabytes in total, on the very near horizon.