Silicon Image, the company whose designs were behind the new Mobile HD Interface effort launched last month, this week says it has a core processor design which will cope with 18 megapixel devices.
The idea is to drop the core into existing system on a chip (SoC) designs to accommodate cameras in handset, in line, in terms of capability, with existing top of the range discrete cameras.
It introduced the camerIC-18, the newest member of its family of camera processor IP cores, which it says is aimed at integration into digital still camera (DSC) and video System-on-a-Chip (SoC) for mobile devices such as cell phones, portable multimedia players (PMPs) and netbooks.
In September we told you that Silicon Image was behind a move backed by Nokia, Samsung, Sony and Toshiba Corporation to create a new standard audio and video interface to connect mobile phones to HDTVs, based around its Mobile High-Definition Link technology. The new standard will work like a USB connector, with a low pin count compared to HDMI cables, and providing power from the TV to the handset so that it re-charges while it plays out HD video.
The new camerIC-18 will support resolutions from 5MP to 18MP, and the design includes bad pixel detection/correction and noise reduction techniques, so that it can be combined with cheaper CMOS sensors commonly found in mobile devices. The camerIC-18 IP core also supports lens shade correction, auto focus measurement, auto white balance and auto exposure through brightness measurement.
The company believes that by 2013, over 95% of handsets will have an integrated digital camera, and over 25% of smartphones will support 5MP or higher resolution cameras.
Traditionally image processing cores have been integrated into the CMOS sensor or into a separate application processor. As mobile devices use smaller foundry processes, the growing trend is for image processing technologies to be integrated into an SoC in an effort to reduce costs and power consumption.
The camerIC-18 IP core has the imaging bandwidth to support HD, 3D, 4K and higher resolution video camcorder functions. A 4K resolution camcorder design incorporating a camerIC-18 IP core and running at 30 frames per second will only require about 700k gates to be implemented in hardware and consumes as little as 125mW of power. Only 30 million instructions per second (MIPS) of CPU time are required to support this hardware design, the company claimed.