Leading players across the HEVC ecosystem have been shaping up lately with early deployments and announcements, although it will not be until 2014 that the full codec will be available, along with commercially available encoder and decoder families to choose from. Early deployments have naturally featured the available encoders and connected TVs or set tops that already support HEVC after its ratification in January 2013, such as France Telecom Orange with Samsung 2013 smart TVs and encoders from French H.264 and HEVC specialist ATEME.
Apart from these early deployments the smart money is on HEVC making its greatest early splash for content delivery over LTE mobile networks, where the appeal will be for handling the explosion in video, whether or not Wi-Fi offload is also deployed to take some of the load off the cellular infrastructure. Another reason for expecting mobile services to lead HEVC adoption is that the devices that will consume content over cellular or Wi-Fi will be tablets and smartphones, which tend to be changed relatively often, speeding up the HEVC adoption process. Ericsson is among those trialing HEVC codecs with the mobile market in mind.
The third use case for HEVC, after IPTV and mobile video, is ultra HD, although that is academic until services are actually available. Yet content discovery and distribution product vendor Rovi has been working with chip maker Broadcom specifically on HEVC playback in the home. Rovi’s contribution is the encoding of content according to the DivX HEVC Certification Program designed to ensure that emerging HEVC devices are all compatible. DivX is a lab specializing in development and standardization of video compression and DRM technologies.
Under the partnership with Rovi, Broadcom will enable playback of DivX HEVC streaming and downloadable content in its recently announced BCM7445 UltraHD home gateway chip. This will be accomplished with the help of Rovi’s DivX software tools for PC-based creation and playback, and an extension to the DivX Certification program to allow customers of the chip to develop mobile and consumer electronics products that support high-quality HEVC playback as quickly as possible
Broadcom’s BCM7445 is based on 28nm process technology and features four 1080p30 real-time transcoders capable of delivering resolution up to 4096×2160 of ultra HD at 60 frames per second. Some tests have indicated that a rate higher than 60 fps will be needed to do justice to ultra HD resolutions, especially for fast moving sports content, but if so, early adopters will have to make do with what the likes of Broadcom have enabled in their first generations.
UltraHD is also the focus of UK based developer of multimedia processing Imagination Technologies in its PowerVR D5500 video decoder designed for ultra-low power consumption. This decoder core can be incorporated in other chips and is an optimized tradeoff between high resolutions and frame rates against minimum silicon area and bandwidth usage.
Just like H.264 a decade earlier, HEVC has come along to take advantage of developments in silicon technology and design to improve compression performance about two times. It also of course exploits advances in compression technique, but some of these alone can and have been incorporated into existing H.264 codecs.
Other of the key encoding/decoding advances are inseparable from hardware developments anyway, notably those around parallel processing.
Since H.264 was conceived, multicore processors have come along with an increasing number of cores, partly because this is a more efficient way of improving overall chip performance, with the emphasis primarily on multi-tasking. But the multicore architecture lends itself equally to parallel processing and HEVC has been designed to exploit that as a necessary step for both improved encoding and decoding efficiency. HEVC also takes account of the greater asymmetry between available encoding and decoding power’ in other words the fact that computational capacity available for encoding has increased more than at the decoding end, given the advent of handheld devices for content consumption on which battery capacity is a severe constraint.
Imagination Technologies’ existing core can decode H.264 1080P30 video at around 10mW consumption, which adds around 6% to battery load when consuming video. The company has not said what its target is for HEVC but it can be seen that the advances in parallel processing are essential, even though the computational complexity has been skewed towards the encoding side.
On average HEVC codecs will be two to three times more complex for decoding and 10 times more so for encoding. Significantly there will be a version of HEVC called ‘low complexity mode’, which is actually slightly less complex than H.264 on the decoding side, aimed at smartphones that do not need as high a bit rate for HD quality anyway. This could dovetail with adaptive bit rate streaming to select streams optimized for this particular HEVC codec.
There will also be a ‘low delay’ configuration capable of low latency operation, aimed at live services where even encoding must be performed in real time. It is here that the parallel processing will really come into own, exploiting new techniques that keep the parallel tasks synchronized and minimize their memory consumption. The aim is to ensure that temporary memory is as close to the processing units during computation as possible, to minimize ‘store/retrieval’ latency.
There are several optional parallel processing tools in HEVC that can be used singly or combined, the main two being Tiles and Wavefront Parallel Processing (WPP). As the name suggests, Tiles entails breaking up the picture into a rectangular grid of regions that can each be both encoded and decoded independently in parallel. Each Tile in turn comprises multiple so called Coding Tree Units (CTUs), which are the basic building blocks of video compression. Under H.264 the maximum size of a CTU was 16 x 16 pixels but with HEVC it can be up to 16 times bigger in area terms, 64 x 64 pixels. This larger size allows internal encoding efficiencies inside each block by focusing on micro areas that are similar, which there is clearly far less scope for at just 16 x 16 pixels.
But the parallelism begins at the CTU block level by keeping adjacent blocks synchronized so that several can be in the process of being analyzed for compression at a given time, with the ability to keep them synchronized as results come in from individual CTUs. This keeps the parallelization process local so that memory demands are kept in check. This process is called WPP because it involves advancing diagonally across the picture frame, moving across multiple CTUs at a time in a process that resembles the advancing of a wave front, even though it has nothing to do with waves.
Then at a larger scale, tiles comprising multiple CTUs can themselves be subject to further compression, so that parallelism can operate at different levels under HEVC. It is achieved at a small scale at the level of CTUs and then at a bigger scale with Tiles. The Tile level also allows random access to specific regions of a picture in a video stream, which could be useful in video search for example.
HEVC is not just about compression efficiency but also focuses on improving quality, as in its support for 10 bit color depths rather than just 8 bit as with H.264. This improves color resolution and rendition to approach closer to the human eye’s exquisite color perception.